Chapter 2

CPU Architecture

Overview of CPU internal design

Introduction

Not all CPUs are created equal. The internal design of a processor — its architecture — determines everything from how fast it runs to what software it can execute. Just as the layout of a city's streets and highways determines how efficiently traffic flows, the architecture of a CPU determines how efficiently data and instructions move through the chip.

In this chapter, we will explore the different families of CPU architecture, the difference between architecture and microarchitecture, and the fundamental design philosophies that have shaped the processors we use every day. Understanding CPU architecture will give you a deep appreciation for why some chips excel at number-crunching while others are optimized for energy efficiency.

How It Works

At the highest level, CPU architecture refers to the Instruction Set Architecture (ISA) — the set of commands a processor understands. The ISA is like a language: every program must be translated into this language before the CPU can execute it. Two programs written in different high-level languages can run on the same CPU as long as both are compiled into the same ISA.

The microarchitecture, on the other hand, is the physical implementation of the ISA — how the transistors are arranged, how data flows through the chip, and how the pipeline stages are organized. Two CPUs can implement the same ISA (e.g., x86) with completely different microarchitectures (e.g., Intel's Core vs. AMD's Zen), resulting in different performance and power characteristics.

Modern CPU architectures are divided into two major philosophies: RISC (Reduced Instruction Set Computer) and CISC (Complex Instruction Set Computer). RISC processors use a small set of simple, uniform instructions that execute in a single clock cycle, while CISC processors provide a larger set of more powerful instructions that may take multiple cycles. The x86 architecture is CISC-based; ARM architecture is RISC-based.

Household Object Analogy

Think of CPU architecture like a kitchen layout. The ISA is the recipe book — it defines the available recipes (instructions) and ingredients (data types). The microarchitecture is the actual kitchen design: where the stove is, how the counter space is organized, and how the chef moves between stations. Two kitchens can use the same recipe book but have completely different layouts — one might be optimized for speed with everything within arm's reach, while another might be designed for large banquets with multiple prep stations. Both can cook the same meals, but with different efficiency.

Deeper Dive

The x86 architecture, developed by Intel in 1978 and later adopted by AMD, has dominated desktop and server computing for over four decades. Its CISC design allows a single instruction to perform complex multi-step operations, which made it easier to program in the early days when memory was scarce and compilers were primitive. Today, modern x86 CPUs internally decode CISC instructions into simpler RISC-like micro-operations, combining the best of both worlds.

ARM (Advanced RISC Machines) architecture, developed by Acorn Computers in the 1980s and now licensed by Arm Holdings, is the most widely used ISA in the world. ARM processors power over 99% of smartphones, along with an increasing number of laptops, servers, and embedded devices. The ARM architecture emphasizes energy efficiency, using a simpler pipeline and fewer transistors per instruction, which translates directly into longer battery life.

Another fundamental architectural concept is pipelining. Instead of waiting for one instruction to complete before starting the next, a pipelined CPU overlaps the stages of multiple instructions. A classic five-stage pipeline includes Fetch, Decode, Execute, Memory Access, and Write-Back. While one instruction is being decoded, the next is being fetched, and the previous one is being executed — dramatically improving throughput.

Advanced

Modern CPU architectures employ superscalar execution, meaning they can issue multiple instructions per clock cycle across several parallel execution pipelines. A typical high-end x86 core might have six or more execution ports: integer ALUs, floating-point units, load/store units, and branch execution units. The CPU's scheduler analyzes the instruction stream and dispatches independent instructions simultaneously.

Out-of-order execution (OoO) further enhances performance by allowing the CPU to execute instructions as soon as their operands are ready, rather than in strict program order. The CPU maintains a reorder buffer that tracks instruction dependencies and commits results in the original program order to ensure correctness. This technique can dramatically improve utilization of execution units when instructions stall on cache misses or data hazards.

The RISC-V architecture represents a new, open-standard ISA that is gaining traction in academia and industry. Unlike x86 and ARM, which are proprietary, RISC-V is freely available, enabling anyone to design and manufacture chips without licensing fees. Its modular design includes a small base integer instruction set plus optional extensions for floating-point, vector processing, cryptography, and more. RISC-V is particularly promising for custom application-specific processors, IoT devices, and emerging AI accelerators.

Vocabulary Table

Term	Definition
Architecture	The overall design and structure of a CPU, including its instruction set and data pathways
Microarchitecture	The physical implementation of an architecture — how transistors and circuits realize the ISA
x86	A CISC-based ISA developed by Intel, dominant in desktop and server processors
ARM	A RISC-based ISA known for energy efficiency, used in most smartphones and increasingly in laptops
RISC	Reduced Instruction Set Computer — uses simple, fixed-length instructions that execute in one cycle
CISC	Complex Instruction Set Computer — uses variable-length instructions that can perform multi-step operations
ISA	Instruction Set Architecture — the contract between software and hardware defining available instructions
Pipeline	A technique where multiple instruction stages (fetch, decode, execute) are overlapped for higher throughput
Superscalar	A CPU design that can issue and execute multiple instructions per clock cycle
RISC-V	An open-standard RISC ISA that anyone can use without licensing fees

Fun Facts

The x86 architecture is backward-compatible all the way to the Intel 8086 from 1978. A modern CPU can still run software written almost 50 years ago.

ARM-based chips sold over 250 billion units by 2024 — more than any other processor architecture in history.

Apple's M-series chips (ARM-based) deliver comparable or better performance than many x86 chips while using significantly less power.

Modern x86 CPUs translate each complex CISC instruction into 1-4 simple RISC-like micro-ops before execution — effectively acting as RISC chips internally.

The first RISC chip, the Berkeley RISC-I (1982), had only 44,500 transistors — about 0.0001% of a modern Apple M3's transistor count.

RISC-V was originally developed at UC Berkeley in 2010 for a short research project — now it is a global open-standard architecture backed by hundreds of companies.

Interactive Diagram

Explore a visual comparison of different CPU architectures and see how pipelines work under the hood.

Open Interactive Diagram

The interactive diagram for this chapter demonstrates CPU Architecture. It shows the internal architecture of a CPU showing the control unit, ALU, registers, and buses.

What to explore:

click each architectural component to learn its role; watch data flow between components during an instruction
CPU architecture defines how the processor is organized internally — the arrangement of control, arithmetic, and memory units determines performance

Chapter Navigation

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